1. Field of the Invention
This invention relates to software implementations of discrete time filters, and in particular to software implementations of a Finite Impulse Response (FIR) filter on a general purpose processor.
2. Description of the Relevant Art
Traditional implementations of discrete time filters for signal processing applications have used a custom Digital Signal Processor (DSP) instruction to implement an N-tap filter. Such a DSP instruction is executed to perform a multiply-accumulate operation and to shift the delay line in a single cycle (assuming the delay line is entirely in zero-wait state memory or on-chip). For example, on a TI320C50 DSP, a finite impulse response (FIR) filter is implemented by successive evaluations of an MACD instruction, each evaluation computing an element, y.sub.n, of the filtered signal vector, i.e., of the output vector, y[K], such that: ##EQU3## where h[N] is the N-tap filter coefficient vector and x[K] is an input signal vector.
Unfortunately, for many portable device applications such as Personal Digital Assistants (PDAs), portable computers, and cellular phones, power consumption, battery life, and overall mass are important design figures of merit. In addition, very small part counts are desirable for extremely-small, low-cost consumer devices. Signal processing capabilities are desirable in many such portable device applications, for example to provide a modem or other communications interface, for speech recognition, etc. However, traditional DSP implementations of such signal processing capabilities create increased power demands, increase part counts, and because of the power consumption of a discrete DSP, typically require larger heavier batteries.